The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, planar transistors have been replaced by three-dimensional fin-like field effect transistors (FinFET) for which the n-type source/drain features and the p-type source/drain features are often formed in separate processes in an effort for improving device performance with decreased feature size. However, there are challenges associated with this fabrication method. In one example, due to structural differences between the n-type and p-type source/drain features, the sequence by which these features are formed may be improved upon to accommodate the fabrication of devices with reduced feature sizes.